CVE-2026-23554
Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
Does this matter?
High impact if exploited, but EPSS currently rates exploitation as unlikely (0.13%). Schedule it in the normal patch cycle and watch for a rise in EPSS or a public exploit.
Description
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
- CVSS 3.1
- 7.8 HIGHCVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H
- EPSS
- 0.13% probability · 3th percentile
- CISA KEV
- Not listed
- Weakness
- CWE-367
- Affected
- xen/xen
- Source
- security@xen.org
References
- https://xenbits.xenproject.org/xsa/advisory-480.htmlPatch, Vendor Advisory
- http://www.openwall.com/lists/oss-security/2026/03/17/6Mailing List, Patch, Third Party Advisory
- http://xenbits.xen.org/xsa/advisory-480.htmlPatch, Vendor Advisory
Source: NVD record, EPSS from FIRST.org, KEV from CISA. Refreshed daily.