SOC status:Duty analyst on shift

UK Cyber Defence
VulnerabilityModified

CVE-2020-24512

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

LOW 3.3EPSS 0.38%

Does this matter?

Lower severity and a low EPSS score (0.38%). Track it; it rarely justifies an emergency change on its own.

Description

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

CVSS 3.1
3.3 LOWCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:L/I:N/A:N
EPSS
0.38% probability · 32th percentile
CISA KEV
Not listed
Weakness
CWE-203
Affected
intel/microcode · debian/debian linux · netapp/fas\/aff bios · netapp/hci compute node bios · netapp/solidfire bios
Source
secure@intel.com

Source: NVD record, EPSS from FIRST.org, KEV from CISA. Refreshed daily.